Free shipping DSP2812 development board 00IC TOP2812 TMS320F2812 Learning DSP kit

Free Shipping DSP2812 Development Board 00IC TOP2812 TMS320F2812 Learning Board DSP Development Kit
  • Seller BETTERSHENGSUN SHENGSUN Store
  • List Price US $130.00piece
  • Sale Price US $130.00piece
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  • Ratings 5.0 (29)

Item Specifics

Test14
Test44
Brand NameBETTERSHENGSUN
is_customizedYes

Product Description

120$/PCS

Product overview
1.1 INTRODUCTION
TOP2812 development board is based on TMS320F2812 DSP and EPM240T100C5 CPLD two development platform for learning and.
1, with more than 20 experimental project, while providing complete schematics, code and common external interface, can be used as individuals, companies, universities and Research Institute for beginners learning and teaching tool.
2, at the same time, out of control signals and CPLD DSP all 80 I/O signals, can be used as two development platform.
3, board hardware design fully consider the factors of EMC, EMI and cooling, installation, the maximum possible leads all the interfaces, so he can also be used as a functional board embedded directly to the users of the products, shorten the product development cycle of user.

.2 packing list (basic)
1, the TOP2812 development board;
2, the XDS100 USB2.0 simulator (DSP simulator)
3, 5V DC regulated power supply;
4, USB-BLASTER download a; (CPLD download)
5, serial straight line;
6, 1602 LCD module;
7, DC motor;
8, step motor;
9, DuPont line ten;
10, 2*40 double needle four root;
11, the 14pin JTAG line of two;
12, USB2.0 cable;
13, the user disk DVD;
14, DSP value learning CD DVD;
15, a transparent plate glass and organic copper pillar
1.3 system resources
• DSP processor TMS320F2812, 32 bit fixed-point high-speed digital processor, the highest frequency of 150M;
• on-chip built-in 128K * 16 FLASH, the programmer can cure the user program conveniently, FLASH encryption;
• on-chip built-in 18K * 16 bit SRAM;
• on-chip built-in 4K * 16 BOOT ROM;
• on-chip built-in 1K * 16 OTP ROM;
• extended 256K * 16 SRAM, IS61LV25616;
• extended 512K * 16 bits FLASH, SST39VF800, convenient for the user to write large programs;
• CPLD using ALTERA MAXII series of EPM240T100C5N (equivalent to 8650 CPLD, the capacity is two times, the early MAX series and can be burned at least 100000 times), available for download interface, users can write their own code;
• 2 8 segment digital tube; wherein a 1 bit digital tube for use with DSP, another 2 digital tube for the use of CPLD;
• provides 8 LED luminous tube, convenient status indication;
• provides 8 independent buttons;
• provide 1 buzzer;
• provides 1 8 bit code switch;
• provide reset circuit, ensure reliable reset, independent reset button, manual reset;
• provides 1 RS232 interface, can be connected to the PC experiment;
• provides 1 CAN2.0 interface, convenient for the user to network;
• provides 16 channels of AD input interface (input range of 0 ~ 3V);
• provide a headphone jack, can easily realize the playback function;
• provide microphone jack, can be conveniently recording function;
• provide 12864 Chinese graphics LCD interface;
• provide 1602 characters LCD interface;
• provide DC motor control interface, anti;
• provides stepper motor control interface, anti;
• provide 6 PWM output interface;
• bus open, data lines, address lines, control lines, special function pin all leads, two times the development of user-friendly;
• power supply directly supplied by an external power supply, more stable and reliable;
• provide high quality independent power switch, power control, convenient operation;
• provide four fixed holes, user-friendly installation fixed;
• physical size: 17 * 11 cm;
1.4 extended interface
DSP bus, AD, DA, EVA, EVB, PWM and all other pins leads, 4 32 pin pin interface, pin spacing of 2.54mm, users can expand the use of;
All 80 I/O • CPLD port through a 4 interface all leads, pin spacing 2.54mm;
DSP JTAG interface, IEEE 1149.1 compliant, of which sixth foot air, pin spacing of 2.54mm, can be used in conjunction with the market for all standard JTAG interface simulator;
CPLD, JTAG interface standard, anti anti plug design, can be connected to ByteBlasterII or USB-Blaster download cable;
• 6 PWM interface extraction, distance between pins 2.54mm;
• DC motor interface extraction, distance between pins 2.54mm;
• stepper motor interface extraction, distance between pins 2.54mm;
• 12864 Chinese graphics LCD interface extraction, 20 core hole seat, pin spacing 2.54mm;
• 1602 characters LCD interface extraction, 16 core hole seat, pin spacing 2.54mm;
• 1 headphone jacks (green);
• 1 microphone jack (pink);
• CAN2.0 bus interface socket, 2 Blue terminal, 5.08mm spacing;
• RS232 standard DB9 port interface socket;
• DC 5V external power input interface;
• DSP mode selection jumper and PLL enable selection jumper, 2.54mm spacing;
The 1.5 code and experimental project
Part DSP
In Experiment 1, the internal timer 0 marquee experiment;
Experiment 2 internal timer 2 alternating light flash experiment;
In Experiment 3, the EV event manager experiment;
Experiment 4 SPI digital tube display;
Experiment 5 GPIO buzzer control experiment;
Experiment 6 external RAM read and write test;
Experiment 7 external FLASH read and write test;
Experiment 8 button control experiment;
Experiment 9 external interrupt control experiment;
The 10.ADC experiment;
The 11.RS-232 interface experiment;
The 12.CAN bus interface experiment;
Experiment 13 audio output test;
Experiment 14 DC motor control experiment;
Experiment 15 stepper motor control experiment;
Experiment 16.1602 character LCD experiment;
Experiment 17.12864 liquid crystal display experiment;
Experiment 18 timer 0 interrupt experiment
Experiment 19 timer 2 interrupt experiment
The experimental 20.EV timer interrupt experiment
The 21.PWM output waveform experiment
The experimental 22.SPI data transceiver experiment
Experiment 23 single beat stepping motor experiment
In experiment 24, double four stepper motor experiment
In experiment 25, eight beat stepper motor experiment
The 26.FFT algorithm experiment
The 27.FIR algorithm experiment
The 28.IIR algorithm experiment
Experiment 29 convolution algorithm experiment
In experiment 30, FIRLMS adaptive filter algorithm experiment
The experimental 31.FLASH burning experiment
The above experimental projects are provided with C language version of the source code, and the corresponding notes.
Part CPLD
Experiment 1 dial switch control experiment;
Experiment 2 light water experiment;
Experiment 3.7 segment digital tube decoder;
Experiment 4 divider experiment;
The 5 keys to control LED experiment;
Experiment 6 dynamic digital tube display;
Experiment 7 counter experiments;
In Experiment 8, the state machine control experiment;
In Experiment 9, the buzzer alarm test;
Experiment 10 music experiment;
The 11.LCD display experiment;
The project uses the VHDL code, the VHDL routine collection and at the same time, more than 700 routines used; Verilog routines in 135 cases, for the user to learn reference.
1.6 related data
Diagram 1 complete (PDF format, which fully consistent with the PCB), to quickly master the application of many practical interface;
C language source code 2 in all experiments, have a detailed Chinese notes;
Methods and tools for 3 programming FLASH, used for curing the user program;
4 chip Manual: provide all chip development board chip data;
5 send the original TI DSP development environment, CCS3.3 software, CCS4/5 software (out of the old version of CCS2.2 for C2000 software);
6 to provide the emulator driver and other DSP Book CD related learning materials;
As Acrobat reader, Bushound 7 USB bus monitoring software, Sscom serial debugging assistant tools;
The 8 gift Altera download cable schematics;
9 a liquid crystal matrix software, development of LCD display procedures necessary for;
The 10 gift TCP/IP protocol volume: Volume 1 ~ 3;
The 11 gift USB specification document;
The 12 gift CAN2.0 specification document;
The 13 U disk system documentation;
14 FAT16, FAT32 system documentation;
The 15 gift UCOS-II in the transplant F2812 source;
16 FFT, FIR library;
The 17 gift of full range of TI chip package library;
18.QuartusII installation uses video tutorial;
19.Altera download line hardware installation video tutorial;
20.QUARTUSII version 5.1.
21.ModelSim software
22.VHDL language routines (700 cases)
23 VHDL tutorial, VHDL programming teaching examples
24 hardware description language examples set (dozens of program source code)
25 VERILOG routines in 135 cases
26 VERILOG tutorial
The 27 gift of scanning books "Altera FPGA_CPLD design (fundamental)" and "Altera FPGA_CPLD" (Advanced)
28 exclusive QuartusII software proficiency necessary -- Chinese version of QuartusII software guide book
29 user manual: one hundred pages, very detailed, including hardware circuit analysis, experimental examples, CCS3.3 quick start guide, TMS320F2812 chip structure and basic system;
The above presented information is for learning, not for commercial purposes!
1.7 typical applications
Teaching application, industrial automation control, UPS, motor control, robot;
Frequency conversion control, automotive, machinery, disk drives, digital filtering;
Vibration analysis, AC servo motor, DC motor control etc..
Brief introduction of XDS100 function
The 00ICXDS100USB simulator is Hefei Zero Zero Electronic Technology Co., Ltd. launched a low cost and high performance DSP development tools, download and debug support TI Piccolo series, TMS320F28XX series DSP under CCS3.3, under CCSv4 can support TMS320C54x, TMS320C55x, TMS320C64x+ and TMS320C674x etc.. Appreciation of the enormous space, is the special simulation debugger is a basic type.
Note, this simulator is produced in accordance with the original TI scheme, different from the market of the XDS100V1 simulator, simulator internal difference is very big. In the CCS3.3, CCS4 and CCS5 were without having to install drivers, plug the simulator automatic recognition. In CCS3.3, to support a variety of computer operating system CCS4 and CCS5, including 32 bit and 64 bit systems WIN7 and WIN8.
00ICXDS100USB emulator supports CCS v3.3/CCS V4 development environment.
Using USB2.0 communication interface, good compatibility, the computer can be used.
The simulation speed is high and no external power supply, support hot plug.
The plastic package, the design has the advantages of beautiful appearance, easy to carry.
Available in 14 pin TI standard JTAG interface, strong versatility.
In support of the WIN2000/XP/VISTA/WIN7 operating system.

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